Semiconductor wafers are produced from crystal ingots by a series of processing steps, each step designed to bring the wafer closer to compliance with a specification for acceptable wafer characteristics. Each step may also prepare the wafer for a next step and/or remove residual damage from an earlier step. Wafer specifications vary depending on the use for which the wafer is destined, but, in general, the wafer must be processed so that its front and back surfaces are flat and defect free.
Flatness is measured in terms of total thickness variation (TTV) across the entire wafer surface and a site flatness characteristic, denoted SFQR, which is a measure of thickness variations within bins or small areas, known as sites, which typically are the same size as the dies for the prospective chips that will be cut from the wafer. Flatness may be measured by a process having a finer degree of resolution, known as nanotopography, which measures peak-to-valley changes within smaller bins, typically 2 mm×2 mm or 10 mm×10 mm, resulting in a characteristic known as height change threshold (HCT). Defects, such as pitting, typically are detected by visual inspection of the wafer surface, e.g., under a haze lamp.
A wafer is first sliced from an ingot or ingot segment by a rotating disc saw or a wire saw, which may also use an abrasive slurry. The wafer is then cleaned, e.g., by ultrasonic cleaning, to remove particles of the wafer, of the saw and/or of the slurry clinging to the surfaces of the wafer. The edge of the wafer is then ground to an exact diameter and the sharp corner of the edge is chamfered into a rounded edge, which is less likely to chip or otherwise lead to fracturing of the wafer.
The wafer is then lapped, typically between two rotating plates and with an abrasive slurry, to make the front and back surfaces flat and parallel to one another. The lapping also removes the surface damage that the saw and saw-slurry, if used, created on the wafer surfaces during the slicing step. The lapping typically improves the flatness of the wafer surfaces and makes them more parallel to one another, and also leaves a signature damage, albeit one less in magnitude than the slicing damage.
After lapping, the wafer typically is chemically etched on both surfaces with either or both of a mixed acid or an alkaline solution to remove the lapping damage. Then, at least the front wafer surface is polished, although the back surface may also be polished, either sequentially or simultaneously with the front, depending on the wafer's intended use. After polishing, the wafer is ready for cleaning and inspection prior to an optional deposition of an epitaxial layer on the front surface and further processing into integrated circuits.
A patent to Xin, U.S. Pat. No. 6,214,704, describes an application of a fine grinding process to the front surface of the wafer after lapping, and also requires that, during this grinding step, the lapping damage is left intact on the back surface of the wafer. After grinding the front surface, and etching only the front surface, Xin discloses, simultaneously polishing the front and back surfaces of the wafer. Xin discloses retaining the damage on the back surface of the wafer for the purpose of facilitating gettering on the back surface of the wafer.
A patent to Vandamme et al., U.S. Pat. No. 6,114,245, also describes an application of a fine grinding process to the front surface of the wafer after the etching that follows lapping of the wafer. Vandamme also describes front side fine grinding in a process not including a lapping step, and double side fine grinding in a process that does not including a lapping step or an etching step.